This invention relates to clock and data recovery circuits, and more particularly, to clock and data recovery circuits with automatic mode switching and override capabilities for use in integrated circuits such as programmable logic devices.
High-speed data communications links are commonly used in modern digital systems to convey data between integrated circuits. Serial data links are often preferred over parallel links, because serial links avoid the problems with skew that are faced when parallel data and clock signals are transmitted across conductive traces and other paths through a system. A serial link with a high-speed data signal and an embedded clock has no skew, because the clock and data travel over the same communications path.
In a typical high-speed serial communications arrangement, a transmitter on an integrated circuit sends high-speed serial data to a receiver on another integrated circuit. The transmitter embeds a clock signal with the serial data. At the receiver, a clock and data recovery (CDR) circuit is used to extract the embedded clock. Once the clock and data recovery circuit has recovered the clock signal from the incoming data stream, the data can be deserialized and distributed to circuitry on the receiving integrated circuit.
Some clock and data recovery circuits use two phase-locked loops to recover the incoming data and clock. A first phase-locked loop locks onto a reference clock signal. Once the reference clock has been acquired, a second phase-locked loop is used to recover the embedded clock and data from the serial data stream.
It would be desirable to be able to provide improved clock and data recovery circuits for use in integrated circuits such as programmable logic devices.